The present invention relates to semiconductor memory circuits. More particularly, the invention relates to a dynamic random access memory utilizing a MOS FET, hereinafter referred to as "a MOST." The memory itself is termed a MOSRAM.
In general, in a MOSRAM of the single-transistor, single-capacitor type, the chip area per bit is made small in order to prevent the total chip area from being larger than practical limits due to the desired large capacity of the memory. Accordingly, because of the small area per bit, a MOSRAM of this general type can store only a small amount of charge per bit. However, the small amount of charge stored per bit in each memory cell results in a small safe operational margin for reading data from the memory and increases the amount of "soft" error due to .alpha. rays. In order to overcome these difficulties, it is necessary that even a MOSRAM having a large capacity be so designed that the amount of charge stored per bit is not overly small.
The amount of charge Q stored in a memory cell in a MOSRAM of the single-transistor, single-capacitor type can, in general, be represented by the following equation: EQU Q=Cs.multidot.Vs (1)
where Cs is the capacitance of the memory cell and Vs is the writing voltage of the memory cell.
As is apparent from the equation (1), the value Q can be increased by increasing the capacitance Cs or the voltage Vs. However, it is not practical to increase the capacitance because it is necessary to minimize the cell area per bit in order to provide a large capacity memory. On the other hand, the voltage Vs may be increased because to do so does not affect the chip area and, accordingly, such a memory may be realized merely by suitably designing the drive circuitry therefor.
FIG. 1 is a circuit diagram showing the arrangement of a conventional circuit for rewriting data into a memory cell. In this circuit, a voltage difference read out of the memory cell is amplified by a sense amplifier and the voltage thus amplified is written back into the memory cell directly. The associated charging circuit is not shown in FIG. 1.
In FIG. 1, reference character BL designates a bit line, MC a memory cell, DC a dummy cell, SA a sense amplifier circuit including a flip-flop, Q1, Q2, Q3 and Q4 MOSTs of the sense amplifier circuit, C1 and C2 signal terminals for activating the sense amplifier circuit, Q5 and Q6 MOSTs for precharging the bit line, C3 and C3 signal terminals for precharging the bit line, C4 a signal line for connecting the bit line to the memory cell, Q7 a MOST in the memory cell, Cs a storage capacitor in the memory cell, and N1, N2, N3, N4 and N5 connection points.
The circuit in FIG. 1 operates as follows. After signals read out of the memory cell MC and the dummy cell DC are transmitted to the bit line BL, the signal terminal C1 is grounded to Vss to activate the sense amplifier circuit SA so that the small signal difference between the connection points N1 and N2 on the bit line is amplified. The bit line BL is maintained precharged to V.sub.DD until a signal from the memory cell MC is transmitted thereto. The MOSTs Q3 and Q4 are provided to prevent a decrease in the potential of the side whose potential is raised after amplification.
If a logical "1" or "H" (high potential) has been stored in the memory cell MC, the connection point N2 is at the high potential; however, it is lower by V.sub.th, corresponding to the threshold voltage of the MOST Q7, than V.sub.DD. Therefore, if the potential on the signal line C4 is V.sub.DD, the potential at the connection point N5 is V.sub.DD -V.sub.th and the maximum potential V.sub.DD -V.sub.th is rewritten into or stored by the capacitor Cs of the memory cell MC.
A circuit for writing the potential V.sub.DD into the memory cell MC during the operation of the circuit has been proposed in the art, an example of which is shown in FIG. 2. The circuit shown in FIG. 2 can be formed by connecting recharge circuits RC to both connection points of the bit line in the circuit shown in FIG. 1. In FIG. 2, reference characters Q8 and Q9 designate MOSTs in the recharge circuit, C5 a signal terminal of the recharge circuit, CP1 a boostrap capacitor in the recharge circuit, and N6 a connection point in the recharge circuit.
The circuit of FIG. 2 operates the same as the circuit of FIG. 1 until the potential V.sub.DD -V.sub.th is rewritten. After the potential rewriting operation, the potential of the signal line C4 is raised to a level higher than V.sub.DD +V.sub.th and the level of a clock pulse applied to the signal terminal C5 is raised to "H" from "L" so that the potential of the connection point N6 is raised to a level higher than V.sub.DD +V.sub.th and the connection point N2 is recharged to V.sub.DD. As the signal line C4 is at a potential higher than V.sub.DD +V.sub.th, the potential V.sub.DD is written through the connection point N5 into the capacitor Cs of the memory cell MC. The recharge circuit RC is recharged only when the connection point N2 is raised to the high potential. When the connection point N2 is set to the zero potential, the connection point N6 is also set to the zero potential and therefore the recharge circuit RC is not recharged. Accordingly, no power is unnecessarily consumed in the recharge circuit RC.
Recently, a large capacitance MOSRAM has been developed which uses a short channel. This device requires a lower V.sub.DD than the circuit described above because of the voltage withstanding property of the MOST. Thus, typically a 5 V power source must be used for a dynamic 64K MOSRAM or 16K MOSRAM of this type. However, in this case, the voltage Vs in the above-described expression (1) is decreased and the amount of charge stored in the memory cell is decreased. This is a serious problem which remains to be solved.
Accordingly, in view of the foregoing, an object of the invention is to provide a circuit for increasing the storage charge of a dynamic MOSRAM.